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2.3. More Complex Examples 37

because the add operation is monotonic. The mechanism which allows this “test”

when “generating” is the set of propagators, which are concurrent processes that are

triggered whenever a domain variable is changed (pruned). The state variable delay is

more involved since one cannot simply add the delay of each function at each generation

step. The delay of a circuit is related to the maximum number of levels an input signal

has to traverse until it reaches the output. This is to say that we cannot use a single

domain variable for describing the delay. Therefore, considering a module with several

inputs, we must compute the delay at its output by computing the maximum delays

from its inputs and adding the module delay. So, we use new fresh variables for the

inputs of a module being generated and assign the maximum delay to the output delay.

This solution is depicted in the following function:

genCirDelay :: state -> delay -> circuit

genCirDelay (A, P, C, D) Dout = (i0, (A, P,C, D))

genCirDelay (A, P, C, D) Dout = (i1, (A, P, C, D))

genCirDelay (A, P, C, D) Dout = (i2, (A, P, C, D))

genCirDelay (A, P, C, D) Dout = (notGate B, (A, P, C, D)) <==

domain [Dout] ((fd_min Dout) + notGateDelay) (fd_max Dout),

genCirDelay (A, P, C, D) Dout == (B, (A, P, C, D))

genCirDelay (A, P, C, D) Dout = (andGate B1 B2, (A, P, C, D)) <==

domain [Din1, Din2] ((fd_min Dout) + andGateDelay)(fd_max Dout),

genCirDelay (A, P, C, D) Din1 == (B1, (A, P, C, D)),

genCirDelay (A, P, C, D) Din2 == (B2, (A, P, C, D)),

domain [Dout] (maximum (fd_min Din1)(fd_min Din2)) (fd_max Dout)

genCirDelay (A, P, C, D) Dout = (orGate B1 B2, (A, P, C, D)) <==

domain [Din1, Din2] ((fd_min Dout) + orGateDelay) (fd_max Dout),

genCirDelay (A, P, C, D) Din1 == (B1, (A, P, C, D)),

genCirDelay (A, P, C, D) Din2 == (B2, (A, P, C, D)),

domain [Dout] (maximum (fd_min Din1)(fd_min Din2)) (fd_max Dout)

Observing the rules for the AND and OR gates, we can see two new fresh domain

variables for representing the delay in their inputs. These new variables are constrained

to have the domain of the delay in the output but pruned with the delay of the cor-

responding gate. After the circuits connected to the inputs had been generated, the

domain of the output delay is pruned with the maximum of the input module delays.

Note that although the maximum is computed after the input modules had been gener-

ated, the information in the given output delay has been propagated to the input delay

domains so that whenever an input delay domain becomes empty, the search branch is

no longer searched and another alternative is tried. Putting together the constraints

about area, power dissipation, cost, and delay is straightforward, since they are or-

thogonal factors that can be handled in the same way. In addition to the constraints

shown, we can further constrain the circuit generation with other factors as fan-in,

fan-out, and switching function enforcement, to name a few. Then, we could submit

the following goal:

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